One of the main challenges in the field of integrated circuits is the realization of electrical connections between the active devices of the system and between the system itself and other interrelated systems, for instance in the complex architecture of an electronic device. Further to the strong miniaturization trend of the active devices obtained in the field of semiconductor technologies, in fact, the structure and dimensions of the interconnect structures have become more and more important. In particular, at some point during the miniaturization trend, the area needed to route the interconnect lines between the active devices exceeded the area occupied by the devices themselves. At this point, continued miniaturization of the active devices did not produce further benefits as the overall dimensions of the system were constrained by the dimensions of the interconnect structures.
In order to overcome this limitation, the concept of multilevel interconnection has been implemented. In particular, according to the multilevel interconnection approach, the area needed by the interconnect lines is shared among two or more levels so as to allow the increase of the functional density of the system, i.e. of the number of interconnected devices per chip area.
Nowadays, multilevel interconnect structures play an important role in the field of integrated circuits because they accomplish the fundamental tasks of providing both electronic connections between the active devices of the system, and electronic connections to bonding pads adapted to provide interconnect points for the finished system. The final properties of the system and, in particular, its structural and electronic properties, strongly depend on the structural and electronic properties of the multilevel interconnect structures.
A schematic example of a multilevel interconnect structure known in the art is shown in FIG. 1. The system comprises a pre-metal dielectric (PMD) level 110, a first metal level 120, an intermetal dielectric (IMD) level 130 and a second metal level 140.
The PMD level 110 provides for the insulation between the upper level of the active devices of the system (not shown in FIG. 1) and the first metal level 120.
The first metal level 120 is patterned so as to exhibit three separate metal regions 121, 122 and 123. In particular, the metal regions 121, 122 and 123 are separated by portions of the IMD level 130. The spacing between the metal regions 121 and 122 and the spacing between the metal regions 122 and 123 measure 1 m or more.
The IMD level 130 provides for the insulation between the first metal level 120 and the second metal level 140 and also for the insulation between the separate metal regions 121, 122 and 123 of the first metal level 120. The IMD level 130 further comprises two funnel-shaped vias 151 and 152 providing the electric connections between the first metal level 120 and the second metal level 140. In particular, the funnel-shaped vias 151 and 152 connect the second metal level 140 with the metal region 122 of the first metal level 120.
The metal regions 121, 122 and 123 as well as the second metal level 140 and the funnel-shaped vias 151 and 152 are made of Aluminum (Al). In particular, as will be explained in detail below, thanks to the dimensions of the system, and thanks especially to the fact that the spacings between the metal regions 121, 122 and 123 of the first metal level 120 measure 1 m or more, the vias 151 and 152 are funnel-shaped and can be, accordingly, filled with Al.
In the following, the method for fabricating the structure shown in FIG. 1 will be described.
The first metal level 120 is formed depositing on the PMD level 110 an Al film by means of sputtering and by subsequently patterning the film by means of dry etching processes. The patterning process is employed to form the separate metal regions 121, 122 and 123.
In order to form the IMD level 130, chemical vapor deposition (CVD) is employed so as to form the silicon dioxide (SiO2) layer 131. In particular, the silicon dioxide layer 131 is formed by the so-called TEOS oxide, i.e. SiO2 obtained by means of thermal TEOS-CVD processes wherein Tetraethyl Orthosilicate (TEOS) is employed as source for SiO2. As shown in the figure, TEOS grows not only above the metal regions 121, 122 and 123, but also in the interspaces between these regions. However, because of the presence of these interspaces, the TEOS layer 131 is not smooth, but it exhibits a stepped structure following the profile of the metal regions 121, 122 and 123. For this reason, spin on glass (SOG) planarization processes are performed in order to fill the gaps 132 formed by the TEOS layer 131 in correspondence to the interspaces between the metal regions 121, 122 and 123 and to smooth the upper surface of the dielectric. In particular, according to the SOG technique, an interlayer dielectric material is applied in liquid form so as to fill narrow spaces without causing voids. The process comprises spinning for obtaining thickness uniformity and curing for hardening the film. Finally, an etchback process is preformed in order to smooth the upper surfaces of both the TEOS layer 131 and of the SOG regions 132 and to make them level so as to obtain a smooth surface for the deposition of a second dielectric layer 133.
The second dielectric layer 133 is formed by means of a TEOS-CVD process so that, similarly to the layer 131, the layer 133 is made of TEOS oxide too.
At this point, the connecting vias 151 and 152 are formed in the intermetal dielectric level 130. In particular, the connecting vias 151 and 152 are opened through the TEOS layers 133 and 131 in correspondence to the metal region 122 of the first metal level 120. The position and dimensions of the vias are established by means of appropriate masks. The connecting vias 151 and 152 are made funnel-shaped as shown in FIG. 1 so as to easily fill them with Al. In particular, the funnel shape of the vias 151 and 152 strongly improves the filling by means of Al inhibiting the formation of voids, seams and/or other defects.
In the art of semiconductor technology, funnel-shaped vias are also referred to as vias with wine-glass-shaped sidewalls and the process for fabricating them can be referred to as wine-glass etch process. Basically, these vias comprise an upper wide portion corresponding to the mouth of the funnel (or to the bowl containing the wine in the wine-glass) and a lower narrow portion corresponding to the output portion of the funnel (or to the stem of the wine-glass).
Funnel shaped vias such as the vias 151 and 152 shown in FIG. 1, are fabricated by means of a two-step etch process: the upper portion of the IMD level is etched by means of an isotropic etch process while the lower portion of the IMD level is etched by means of an anisotropic etch process. In particular, the isotropic etch process allows the formation of the upper wide portion of the funnel. The upper wide portion of the funnels 151 and 152 comprise the side walls 151a and 151b, and 152a and 152b, respectively, exhibiting low slope. The anisotropic etch process allows the formation of the lower narrow portion of the funnel. The lower narrow portion of the funnels 151 and 152 comprise the steep side walls 151c and 151d, and 152c and 152d, respectively. Since the IMD level 130 in correspondence to the metal region 122 is formed by the first dielectric layer 131 comprising TEOS oxide and the second dielectric layer 132 comprising TEOS oxide as well, both the isotropic etch process and the anisotropic etch process are performed on the TEOS oxide. For this reason, the combination of isotropic etch step and anisotropic etch step allows the formation of well-defined vias exhibiting regular funnel shapes.
At this point, further metal deposition is employed for filling the vias and for forming the second metal level 140 in electric contact with the first metal level 120. In particular, Titanium (Ti) is firstly deposited as liner material on the side walls of the vias 151 and 152 and as adhesive material on the upper surface of the TEOS layer 133. Finally, Al is deposited so as to fill the vias and to form the second metal level 140.
The structure and the dimensions of the system shown in FIG. 1 are compatible with the SOG planarization process and with the formation of funnel-shaped vias to be filled with Al. In particular, since the spacings between the metal regions 121, 122 and 123 of the first metal level 120 measure 1 m or more, they can be filled by TEOS oxide (the layer 131) and SOG dielectric material (the volumes 132). Accordingly, the vias 151 and 152 are dug through a double layer of TEOS oxide (the layers 133 and 131) so that the funnel shape can be easily made by means of the two-step etch process comprising an isotropic step and an anisotropic step as described above.
FIG. 2 schematically displays an example of a multilevel interconnect structure for a system with submicron spacings. In particular, the system shown in FIG. 2, comprises a PMD level 210, a first metal level 220, a IMD level 230 and a second metal level 240. The first metal level 220 is made of Al and it comprises three separate metal regions 221, 222 and 223. Both the spacing between the metal regions 221 and 222 and the spacing between the metal regions 222 and 223 measure less than 1 m.
Since these spacings measure less than 1 m, it is not possible to fill them by means of TEOS oxide. In particular, TEOS oxide is not adapted to fill such narrow spaces because it leads to the formation of an unacceptable level of voids and defects. For this reason, TEOS oxide is replaced by HDP oxide, i.e. by SiO2 deposited by means of High Density Plasma (HDP) deposition. As it is known in the art, HDP processes allow filling narrow spaces such as the spacings between the regions 221, 222 and 223 shown in FIG. 2 with an acceptable level of voids and defects.
Accordingly, the first dielectric layer 231 of the IMD level 230 is formed by HDP oxide. The planarization is performed by means of the CVD deposition of a second dielectric layer 232 of TEOS oxide and of chemical mechanical polishing (CMP) processes of the upper surface of this layer. As can be seen in FIG. 2, TEOS oxide of the layer 232 fills the depressions of the HDP layer 231 in correspondence to the spacings between the metal regions 221, 222 and 223 and provides for an upper smooth surface for the further deposition of the second metal level 240.
The system shown in FIG. 2 exhibits three vias 251, 252 and 253 electrically connecting the second metal level 240 with the metal region 222 of the first metal level 220. As can be seen in FIG. 2, the vias 251, 252 and 253 are not funnel shaped. On the contrary, they exhibit a frustoconical-like shape with steep side walls 251a, 251b, 252a, 252b, 253a, 253b having a slope of 85° or more.
There are mainly two reasons why the vias 251, 252 and 253 are not made funnel-shaped in this case.
A first reason concerns the space required for the formation of funnel-shaped vias. As can be clearly seen comparing for example FIG. 1 with FIG. 2, the upper portions of the funnel-shaped vias 151 and 152 require much more space than the upper portions of the frustoconical-like vias 251, 252 and 253. Accordingly, the frustoconical-like vias have been preferred in order to reduce the devices' overall size.
A second more important reason concerns the incompatibility of the structure of the IMD level 230 of the system shown in FIG. 2 with the two-step etch process necessary for the formation of the funnel-shaped vias. In particular, in order to form funnel-shaped vias through the IMD level 230, it would be necessary to perform the two-step etch process through the TEOS layer 232 and the HDP layer 231. It has been observed that the isotropic step of the two-step etch process causes the formation of irregular and unreliable structures exhibiting a high number of defects. This is in particular due to the different etch rates of the TEOS layer 232 and the HDP layer 231 during the isotropic etch process performed for the formation of the upper wide portion of the funnel-shaped vias. Moreover, the presence of the interface between the TEOS layer 232 and the HDP layer 231 in the region etched by means of the isotropic etch process is critical because this region is subject to unexpected behaviors during the isotropic etch process which give rise to the uncontrollable formation of defects and irregularities. The formation irregularities and defects in the structure of the vias is undesired because it can lead to electric failures and, in general, to unreliable devices.
The vias formed in the IMD level 230 having a structure as shown in FIG. 2 comprising a first dielectric layer 231 of HDP oxide and a second dielectric layer 232 of TEOS oxide are fabricated by means of a single step anisotropic etch process which gives rise to the steep side walls and, ultimately, to the frustoconical-like vias.
These vias cannot be filled with Al because of their shape. In particular, filling frustoconical-like vias with Al would give rise to the formation of an unacceptable level of defects such as voids or seams. For this reason, the vias 251, 252 and 253 are filled with Tungsten (W). In particular, a liner layer of Ti or Titanium Nitride (TiN) is firstly formed on the steep side walls of the vias, and, finally, the vias are filled with W.
After W deposition for filling the vias, etch back processes or chemical mechanical polishing processes are performed in order to planarize the upper surface of the system prior to the formation of the second metal level 240.
The second metal level 240 is formed by depositing a Ti adhesion layer followed by the deposition of Al.
Although the systems such as the one shown in FIG. 2 are widely employed because they guarantee a high level of miniaturization, they still exhibit some problems and drawbacks. In particular, the electrical resistance of the vias filled with W is 10-15 times higher than the electrical resistance of the vias filled with Al. Accordingly, when high currents flow through high resistance vias, high power is dissipated and the temperature of the system increases so that the risk of damage or destruction of the system is very high. This is for example the case for Bipolar-CMOS-DMOS (BCD) devices wherein very low top vias resistance has to be guaranteed. These devices can be employed, in fact, for audio power amplifiers wherein robustness to short circuit tests must be guaranteed. In these extreme conditions, very high currents (even of the order of 100 A) flow in the device for a short time (approximately 1 ms) until a big capacitor is charged, and very high power can be dissipated if the vias exhibit high resistance. This can lead to the destruction of the electronic component because of the heat developed.
Accordingly, it would be desirable to provide a method for the formation of multilevel interconnect structures allowing overcoming these problems. In particular, it would be desirable to provide a method for the formation of multilevel interconnect structures comprising funnel-shaped vias adapted to be filled with Al even for devices exhibiting submicron spacings in at least one of the conducting levels.